Image sensors having pixels with dual-output circuits therein

ABSTRACT

An image sensor pixel includes a substrate, a photodiode and a pixel circuit in the substrate. The pixel circuit includes a transfer element, which is electrically connected between the photodiode and a floating diffusion node that accumulates electrical charges generated by the photodiode in response to light incident the substrate, and a driving element, which is electrically connected to the floating diffusion node. An output circuit is also provided, which is electrically connected between a column line and the pixel circuit. The output circuit includes a switching element electrically connected to an output terminal of the driving element, a primary capacitor electrically connected to the switching element, a secondary capacitor, which is selectively connected to or disconnected from the switching element based on an on/off switching state of a first enable element, and a first selection element electrically connected between the switching element and the column line.

REFERENCE TO PRIORITY APPLICATION

This application claims the benefit under 35 USC 119(a) to Korean PatentApplication No. 10-2020-0074099, filed Jun. 18, 2020, the disclosure ofwhich is hereby incorporated herein by reference.

BACKGROUND 1. Field

The present inventive concept relates to integrated circuit devices and,more particularly, to image sensor devices.

2. Description of Related Art

Image sensors are typically semiconductor-based sensors that receivelight and generate electrical signals in response to the light. Thesesensors may include pixel arrays having a plurality of pixels, logiccircuits that drive the pixel arrays and generate image data, and thelike. A logic circuit may control an image sensor using a global shuttermethod in which image data is obtained by simultaneously exposing aplurality of pixels to light. An image sensor operating in a globalshutter mode may remove image wobble (a/k/a the “jello effect”) and maycapture an exact shape of a subject and output the captured subjectshape as image data.

SUMMARY

Example embodiments provide an image sensor in which noisecharacteristics, operating speed, and the quality of a resulting imagemay be improved, by using capacitors in respective pixels to operate ina global shutter mode, and by varying the capacity of the capacitors asrequired.

According to an example embodiment, an image sensor is provided, whichincludes a plurality of pixels. Each of the plurality of pixelsincludes: (i) at least one photodiode that is configured to generateelectrical charges in response to light, (ii) a pixel circuit thatincludes a transfer element connected between the photodiode and afloating diffusion node (in which the electrical charges areaccumulated), and a driving element connected to the floating diffusionnode, (iii) a first output circuit connected between a first column lineand the pixel circuit, and including a first switching element connectedto an output terminal of the driving element, a first primary capacitorconnected to the first switching element, a first secondary capacitorconnected to or disconnected from the first switching element based onan on/off switching of a first enable element, and a first selectionelement connected between the first switching element and the firstcolumn line, and (iv) a second output circuit connected between thepixel circuit and a second column line, different from the first columnline, and including a second switching element connected to the outputterminal of the driving element, a second primary capacitor connected tothe second switching element, a second secondary capacitor connected toor disconnected from the second switching element based on an on/offswitching of a second enable element, and a second selection elementconnected between the second switching element and the second columnline.

According to another example embodiment, an image sensor is provided,which includes an array of pixels, and a logic circuit configured todrive the pixel array to obtain image data. Each of the plurality ofpixels includes: (i) a photodiode generating electrical charges inresponse to light, (ii) a transfer element connected between thephotodiode and a floating diffusion node, which accumulates theelectrical charges, (iii) a driving element that is connected to thefloating diffusion node and generates an output voltage by amplifying avoltage of the floating diffusion node, (iv) a first output circuitconnected between a first column line and the driving element, andincluding a first switching element, a first capacitor connected to thefirst switching element, and a first selection element connected betweenthe first capacitor and the first column line, and (v) a second outputcircuit connected between the driving element and a second column line,different from the first column line, and including a second switchingelement, a second capacitor connected to the second switching element,and a second selection element connected between the second capacitorand the second column line. Advantageously, the logic circuit sets thefirst capacitor to have a first capacity when intensity of light is afirst intensity, and sets the first capacitor to have a second capacity,smaller than the first capacity, when the intensity of light is a secondintensity greater than the first intensity.

According to an example embodiment, an image sensor includes a pixelarray including a plurality of pixels, and a logic circuitsimultaneously exposing the plurality of pixels to light for an exposuretime and obtaining image data. Each of the plurality of pixels includesa photodiode, a pixel circuit connected to the photodiode and generatinga reset voltage and a pixel voltage, a first output circuit including afirst capacitor storing the reset voltage, and connected between a firstcolumn line and the pixel circuit, and a second output circuit includinga second capacitor storing the pixel voltage, and connected between asecond column line and the pixel circuit. The logic circuit adjusts acapacity of each of the first capacitor and the second capacitor, basedon the exposure time.

BRIEF DESCRIPTION OF DRAWINGS

The above and other aspects, features, and advantages of the presentinventive concept will be more clearly understood from the followingdetailed description, taken in conjunction with the accompanyingdrawings, in which:

FIG. 1 is a schematic block diagram of an image sensor according to anexample embodiment;

FIG. 2 is a diagram provided to illustrate the operation of an imagesensor according to an example embodiment;

FIG. 3 is a schematic circuit diagram of a pixel included in an imagesensor according to an example embodiment;

FIGS. 4 to 6 are diagrams provided to illustrate the operation of animage sensor according to example embodiments;

FIG. 7 is a schematic circuit diagram of a pixel included in an imagesensor according to an example embodiment;

FIG. 8 is a schematic block diagram of an image sensor according to anexample embodiment;

FIG. 9 is a diagram provided to illustrate the operation of an imagesensor according to an example embodiment;

FIGS. 10 to 12 are views provided to illustrate the operation of animage sensor according to an example embodiment;

FIG. 13 is a diagram provided to illustrate an operation of an imagesensor according to an example embodiment;

FIGS. 14 to 16 are views provided to illustrate the operation of animage sensor according to an example embodiment;

FIG. 17 is a diagram illustrating a portion of pixels included in animage sensor according to an example embodiment;

FIGS. 18 and 19 are diagrams schematically illustrating image sensorsaccording to example embodiments;

FIG. 20 is a diagram illustrating a portion of pixels included in animage sensor according to an example embodiment;

FIGS. 21 and 22 are views illustrating a portion of pixels included inan image sensor according to an example embodiment; and

FIGS. 23 and 24 are diagrams schematically illustrating electronicdevices including an image sensor according to example embodiments.

DETAILED DESCRIPTION

Hereinafter, example embodiments will be described with reference to theaccompanying drawings.

FIG. 1 is a schematic block diagram of an image sensor according to anexample embodiment. Referring to FIG. 1, an image sensor 1 may include apixel array 10, a logic circuit 20 and the like. The pixel array 10 mayinclude a plurality of pixels PX disposed in an array shape in aplurality of rows and a plurality of columns. Each of the plurality ofpixels PX may include at least one photoelectric conversion element thatgenerates electrical charge in response to incident light, and aplurality of elements that generate a pixel signal corresponding to anelectrical charge generated by the photoelectric conversion element. Thephotoelectric conversion element may be formed of a semiconductormaterial or an organic material, and may include, for example, aphotodiode.

In some embodiments, each of the pixels PX may include a floatingdiffusion node, a transfer transistor, a reset transistor, a drivingtransistor, and a selection transistor. However, the configuration ofthe pixels PX may be changed according to example embodiments of theinvention. For example, each of the pixels PX may include an organicphotodiode including an organic material(s), or may be implemented as adigital pixel. When the pixels PX are implemented as digital pixels,each of the pixels PX may include an analog-to-digital converter foroutputting a digital pixel signal.

The logic circuit 20 may include circuits for controlling the pixelarray 10. For example, the logic circuit 20 may include a row driver 21,a readout circuit 22, a column driver 23, a control logic 24, and thelike. The row driver 21 may drive the pixel array 10 in the units of rowlines. For example, the row driver 21 may generate a transfer controlsignal for controlling transfer transistors of the respective pixels PX,and a selection control signal for controlling selection transistors,etc. to input the generated signals to the pixel array 10 in the unitsof row lines. In addition, the row driver 21 may simultaneously inputreset control signals for controlling the reset transistors to theentire pixel array 10 to simultaneously reset the pixels PX and exposethe pixels to light. In this case, the image sensor 1 may operate in aglobal shutter method.

The readout circuit 22 may include a correlated double sampler (CDS), ananalog-to-digital converter (ADC), or the like. The correlated doublesamplers may be connected to the pixels PX through column lines.According to example embodiments, the pixels PX may be respectivelyconnected to two or more analog-to-digital converters through two ormore column lines. The correlated double samplers may read a pixelsignal through column lines from pixels PX connected to a row lineselected by a row line selection signal of the row driver 21. Theanalog-to-digital converter may convert the pixel signal detected by thecorrelated double sampler into a digital pixel signal and transmit theconverted signal to the column driver 23.

The column driver 23 may include a latch capable of temporarily storinga digital pixel signal, or a buffer circuit and an amplifying circuit,and may process a digital pixel signal received from the readout circuit22. The row driver 21, the readout circuit 22, and the column driver 23may be controlled by the control logic 24. The control logic 24 mayinclude a timing controller for controlling the operation timing of therow driver 21, the readout circuit 22, and the column driver 23.

Among the pixels PX, pixels PX disposed in the same position in thefirst direction (a traversal direction) may share column lines with eachother. For example, pixels PX disposed in the same position in thesecond direction (a longitudinal direction) are simultaneously selectedby the row driver 21 during a readout operation, and may output pixelsignals through column lines. In an example embodiment, the readoutcircuit 22 may simultaneously obtain a pixel signal from the pixels PXselected by the row driver 21 through column lines. The pixel signal mayinclude a reset voltage and a pixel voltage, and the pixel voltage maybe a voltage in which charge generated in response to light in each ofthe pixels PX is reflected in the reset voltage.

When the image sensor 1 operates in a global shutter method, each of thepixels PX may include storage elements, such as capacitors, which arecapable of storing the reset voltage and the pixel voltage. When thecapacitors have a relatively large capacity, noise characteristics ofthe pixel signal may be improved, but the time required to store thereset voltage and the pixel voltage in the capacitors can increase,which means the operation speed of the image sensor 1 may be slowed.Conversely, reducing the capacity of the capacitors may improve theoperation speed of the image sensor 1, but noise characteristics maydeteriorate.

In an example embodiment, the capacity of capacitors included in each ofthe pixels PX may be adjusted, thereby advantageously implementing anoperation optimized for a respective imaging environment. For example,in a high illuminance environment in which noise is not expected to beexcessive, the capacity of the capacitors may be reduced to secure afast operation speed of the image sensor 1; however, in a lowilluminance environment, the capacity of the capacitors may be increasedto improve the noise characteristics but at the cost of possibly sloweroperating speed.

FIG. 2 is a diagram provided to illustrate the operation of an imagesensor according to an example embodiment. FIG. 2 may be a diagramprovided to illustrate a global shutter operation of the image sensor 1.Referring to FIGS. 1 and 2 together, photodiodes of a plurality ofpixels PX included in the pixel array 10 may be simultaneously resetduring a reset time TRST. For example, the row driver 21 may reset thephotodiodes by turning on the reset elements included in the pixels PXto remove electrical charges from the photodiodes.

When the photodiodes are reset, the photodiodes included in theplurality of pixels PX may be exposed to light during the exposure timeT_(EX) to generate an electrical charge. For example, the exposure timeT_(EX) may be determined by an operating environment of the image sensor1, a shutter speed, an aperture value, and the like.

The electric charges generated by the photodiodes in response to lightduring the exposure time T_(EX) may be stored in capacitors included inthe pixels PX. Accordingly, the exposure time T_(EX) may include a timeat which the photodiodes are exposed to light and a time at which theelectrical charge generated by the photodiodes is stored in thecapacitors. For example, a reset voltage in which charges generated byphotodiodes are not reflected may be stored in a first capacitor, and apixel voltage in which charges generated by photodiodes are reflected inthe reset voltage may be stored in a second capacitor different from thefirst capacitor.

When the exposure time T_(EX) elapses, the row driver 21 may scan theplurality of respective row lines. The readout circuit 22 may perform areadout operation for the plurality of respective pixels PX according toan order in which the row driver 21 scans the plurality of row lines.The readout circuit 22 may read the reset voltage and the pixel voltagestored in the plurality of respective pixels PX during a readout timeT_(RO).

FIG. 3 is a schematic circuit diagram of a pixel included in an imagesensor according to an example embodiment. Referring to FIG. 3, in animage sensor according to an example embodiment, a pixel 100 may includea pixel circuit 105 connected to a photodiode PD, a first output circuit110 connected to the pixel circuit 105, a second output circuit 120connected to the pixel circuit 105, and the like. The first outputcircuit 110 and the second output circuit 120 may be connected to thepixel circuit 105 in parallel.

The pixel circuit 105 may include a floating diffusion node FD, atransfer element TX, a reset element RX, a driving element DX, a biaselement BX, and the like. The floating diffusion node FD may be a nodein which charges generated by the photodiode PD are accumulated, and thetransfer element TX may be connected between the floating diffusion nodeFD and the photodiode PD. When the transfer element TX is turned on by atransfer control signal TG, electrical charges generated by thephotodiode PD may move and may be accumulate in the floating diffusionnode FD.

The reset element RX may be connected between a power node 101 supplyinga power voltage VDD and the floating diffusion node FD. When the resetelement RX is turned on by a reset control signal RG, the electricalcharge of the floating diffusion node FD is removed and the voltage ofthe floating diffusion node FD may be reset.

The driving element DX includes a gate electrode connected to thefloating diffusion node FD, and may operate as a source-followeramplifier. The driving element DX may amplify and output the voltage ofthe floating diffusion node FD, and the first output circuit 110 and thesecond output circuit 120 may be connected to an output terminal of thedriving element DX. Further, the driving element DX is connected to thebias element BX that supplies a bias voltage V_(BIAS), and may receive acurrent required for operation through the bias element BX. The biaselement BX may be turned on while the driving element DX is operated bythe bias control signal BG.

The first output circuit 110 may be connected between the pixel circuit105 and a first column line COL1. The first output circuit 110 mayinclude a first switching element SW1, a first primary capacitor MC1, afirst secondary capacitor VC1, a first selection element SX1, a firstoutput driving element DX1 and the like. The first secondary capacitorVC1 may be connected to a first enable element EX1 in series, and thefirst secondary capacitor VC1 and the first enable element EX1 may beconnected to the first primary capacitor MC1 in parallel.

The first primary capacitor MC1, the first enable element EX1, and thefirst secondary capacitor VC1 may provide a first capacitor of the firstoutput circuit 110. When the first enable element EX1 is turned off,only the first primary capacitor MC1 is connected to the first switchingelement SW1, and when the first enable element EX1 is turned on, thefirst primary capacitor MC1 and the first secondary capacitor VC1 may beconnected to the first switching element SW1 together. Accordingly, thecapacity of the first capacitor may change based on the on/off switchingof the first enable element EX1.

The first output driving element DX1 receives the power voltage VDD, anda gate of the first output driving element DX1 may be connected to thefirst switching element SW1. Accordingly, the first output drivingelement DX1 may operate as a source-follower amplifier based on thevoltage stored in the first primary capacitor MC1 (or the first primarycapacitor MC1 and the first secondary capacitor VC1). The firstselection element SX1, which is connected between the first column lineCOL1 and the first output driving element DX1, may be controlled by afirst selection signal SEL1.

The second output circuit 120 may be connected between the pixel circuit105 and a second column line COL2. The second output circuit 120 mayinclude a second switching element SW2, a second primary capacitor MC2,a second secondary capacitor VC2, a second selection element SX2, asecond output driving element DX2, and the like. The configuration andoperation of the second output circuit 120 may be similar to those ofthe first output circuit 110. For example, the second primary capacitorMC1, a second enable element EX2, and the second secondary capacitor VC2may provide a second capacitor of the second output circuit 120, and thecapacity of the second capacitor may be change based on the On/Offswitching of the second enable element EX2.

In an example embodiment, the first output circuit 110 may sample thereset voltage output from the pixel circuit 105, and the second outputcircuit 120 may sample the pixel voltage output from the pixel circuit105. For example, the first switching element SW1 may be turned onbefore the floating diffusion node FD is reset and the transfer elementTX is turned on, and the reset voltage may be sampled to the firstcapacitor. The second switching element SW2 is turned on after thetransfer element TX is turned on and the charge of the photodiode PDmoves to the floating diffusion node FD, and the pixel voltage may besampled to the second capacitor.

The first and second output circuits 110 and 120 may simultaneouslyoutput the reset voltage and the pixel voltage. In detail, while thefirst output circuit 110 outputs the reset voltage to the first columnline COL1, the second output circuit 120 may output the pixel voltage tothe second column line COL2. For example, the first column line COL1 maybe connected to a first analog-to-digital converter, and the secondcolumn line COL2 may be connected to a second analog-to-digitalconverter. The logic circuit of the image sensor may calculate adifference between a first digital signal output from the firstanalog-to-digital converter and a second digital signal output from thesecond analog-to-digital converter to obtain image data of the pixel100.

The first primary capacitor MC1 may have a smaller capacity than thefirst secondary capacitor VC1. Similarly, the second primary capacitorMC2 may have a smaller capacity than the second secondary capacitor VC2.According to example embodiments, capacities of the first primarycapacitor MC1 and the second primary capacitor MC2 may be the same ordifferent from each other. Similarly, capacities of the first secondarycapacitor VC1 and the second secondary capacitor VC2 may be the same ordifferent from each other.

Referring to the first output circuit 110 as an example, when the firstenable element EX1 is turned off, only the first primary capacitor MC1may be connected to the first switching element SW1. Accordingly, thecapacity of the first output circuit 110 for sampling the reset voltageoutput from the driving element DX is reduced, and the sampling time maybe shortened, while noise based on the on/off switching operation of thefirst switching element SW1, or the like, may increase. Conversely, whenthe first enable element EX1 is turned on, the capacity of the firstoutput circuit 110 increases by the first secondary capacitor VC1, sothat the sampling time increases, but noise based on the on/offswitching operation of the first switching element SW1 may beadvantageously removed. The operation of the second output circuit 120may also be similarly understood.

The logic circuit of the image sensor may determine the capacity of eachof the first capacitor and the second capacitor in consideration of atleast one of various parameters such as light intensity, exposure time,and sensitivity. For example, when the light intensity is a firstintensity, the first capacitor may be set to have a first capacity, andwhen the light intensity is a second intensity greater than the firstintensity, the first capacitor may be set to have a second capacity,lower than the first capacity. Similarly, when the light intensity isthe first intensity, the second capacitor may be set to have a thirdcapacity, and when the light intensity is the second intensity, thesecond capacitor may be set to have a fourth capacity lower than thethird capacity. The first to fourth capacities may be respectivelydetermined based on respective capacities of the first primary capacitorMC1, the first secondary capacitor VC1, the second primary capacitorMC2, and the second secondary capacitor VC2. As an example, when thefirst and second primary capacitors MC1 and MC2 have the same capacitiesand the first and second secondary capacitors VC1 and VC2 have the samecapacities, the first and third capacities may be the same, and thesecond and fourth capacities may be the same.

As another example, the logic circuit may compare the exposure time witha predetermined reference time to set capacities of each of the firstcapacitor and the second capacitor. For example, when the exposure timeis longer than the reference time, the capacities of the first capacitorand the second capacitor may be set to be relatively large, and when theexposure time is shorter than the reference time, the capacities of thefirst capacitor and the second capacitor may be set relatively small.Alternatively, the capacities of the first capacitor and the secondcapacitor may be determined according to an ISO value representing thesensitivity. In an example embodiment, when the ISO value is less than apredetermined reference value, the capacities of the first capacitor andthe second capacitor may be reduced, and when the ISO value is greaterthan the reference value, the capacities of the first capacitor and thesecond capacitor may be increased. However, this is only an exampleembodiment, and the capacity of the first capacitor and the secondcapacitor may also be determined by the logic circuit in considerationof other various parameters.

FIGS. 4 to 6 are diagrams provided to illustrate the operation of imagesensors according to example embodiments. Hereinafter, for convenienceof description, the operation of the image sensor will be described withreference to the sensor 100 of FIG. 3. First, referring to FIG. 4, thereset element RX and the transfer element TX are turned on by the resetcontrol signal RG and the transfer control signal TG, and thus, thefloating diffusion node FD and the photodiode PD may be reset. When thereset element RX and the transfer element TX are turned off, a firstexposure time EIT1 starts, and during the first exposure time EIT1, thephotodiode reacts to light to generate electrical charges. During thefirst exposure time EIT1, the transfer element TX maintains a turned-offstate, and the reset element RX is turned on at least one time or moreto reset the voltage of the floating diffusion node FD again. When thereset element RX is turned off, the first switching element SW1 isturned on by a first switch control signal SG1 to store the resetvoltage in the first output circuit 110. When the first exposure timeEIT1 starts, the bias element BX may be turned on by a bias controlsignal BG so that the driving element DX of the pixel circuit 105 mayoperate. The bias element BX may be turned on during a storage time STfor storing the reset voltage and the pixel voltage.

The time at which the first switching element SW1 is turned on may bedefined as a reset sampling time RST. In the example embodimentillustrated in FIG. 4, together with the first switching element SW1,the first enable element EX1 may also be turned on. Accordingly, thereset voltage may be stored in the first primary capacitor MC1 and thefirst secondary capacitor VC1.

Referring to FIG. 4, the first switching element SW1 and the secondswitching element SW2 may be turned on together. Accordingly, the resetvoltage may also be stored in the second output circuit 120. Since thesecond enable element EX2 is turned on together with the secondswitching element SW2, the reset voltage may be stored in the secondprimary capacitor MC2 and the second secondary capacitor VC2.

When the first exposure time EIT1 ends, the transfer element TX isturned on by the transfer control signal TG, and the electrical chargegenerated by the photodiode PD during the first exposure time EIT1 maymove to the floating diffusion node FD. When electrons are the maincharge carriers, the voltage of the floating diffusion node FD maydecrease from the reset voltage. The first switching element SW1 may beturned off before the transfer element TX is turned on, for example,before the first exposure time EIT1 ends. Accordingly, before theelectrical charge of the photodiode PD moves to the floating diffusionnode FD, the first output circuit 110 may be separated from the pixelcircuit 105.

On the other hand, the second switching element SW2 may maintain theturned-on state even while the first exposure time EIT1 ends and thetransfer element TX is turned on so that the electrical charge of thephotodiode PD moves to the floating diffusion node FD. When the transferelement TX is turned off, the pixel voltage determined by electricalcharges transferred from the photodiode PD may be stored in the secondoutput circuit 120 during a pixel sampling time PIX. For example, in thesecond output circuit 120, the voltages of the second primary capacitorMC2 and the second secondary capacitor VC2 may be reduced by electricalcharges accumulated in the floating diffusion node FD.

And, when the pixel sampling time PIX elapses, the bias element BX maybe turned off. Thereafter, a readout operation may be performed during areadout time RT at which the first selection element SEL1 and a secondselection element SEL2 are turned on. The readout operation may includecomparing each of the reset voltage stored in the first output circuit110 and the pixel voltage stored in the second output circuit 120 with aramp voltage RMP, and converting the comparison result into a digitalsignal by the analog-to-digital converter. For example, a first samplerconnected to the first column line COL1 may compare the reset voltageand the ramp voltage RMP and may output the comparison result to thefirst analog-to-digital converter. Also, a second sampler connected tothe second column line COL2 may compare the pixel voltage and the rampvoltage RMP and output the comparison result to the secondanalog-to-digital converter. Accordingly, the readout operations for thefirst output circuit 110 and the second output circuit 120 may besimultaneously performed. During the read-out time RT, the bias elementBX is turned on to supply a bias current required for a read-outoperation.

In the example embodiment illustrated in FIG. 4, the reset voltage maybe stored in the first primary capacitor MC1 and the first secondarycapacitor VC1 during the storage time ST, and the pixel voltage may bestored in the second primary capacitor MC2 and the second secondarycapacitor VC2 during the storage time ST. Accordingly, until the readoutoperation is terminated, the first enable element EX1 and the secondenable element EX2 may maintain a turned-on state.

On the other hand, unlike the example embodiment illustrated in FIG. 4,during the storage time ST, the second switching element SW2 may beturned on at a timing different from that of the first switching elementSW1. As an example, the second switching element SW2 may be turned onafter the transfer element TX is turned on and the electrical charge ofthe photodiode PD moves to the floating diffusion node FD.

Next, referring to FIG. 5, the photodiode PD may be exposed to lightduring a second exposure time EIT2 shorter than the first exposure timeEIT1 to generate electrical charges. In an example embodiment, theexample embodiment described with reference to FIG. 4 may be an exampleembodiment for describing the operation of the image sensor in alow-illuminance environment, for example, an imaging environment inwhich the intensity of light is relatively weak. On the other hand, theexample embodiment described with reference to FIG. 5 may be an exampleembodiment for describing the operation of the image sensor in ahigh-illuminance environment, for example, an imaging environment inwhich the intensity of light is relatively strong.

In an imaging environment in which the intensity of light is strong,more charges may be generated in the photodiode PD than in an imagingenvironment in which the intensity of light is weak. Accordingly, asillustrated in FIG. 5, the second exposure time EIT2 may be set to beshorter than the first exposure time EIT1. As the second exposure timeEIT2 is set to be relatively short, the reset sampling time RST at whichthe first output circuit 110 samples the reset voltage may be reducedcompared to the example embodiment illustrated in FIG. 4. According toexample embodiments, the pixel sampling time PIX at which the secondoutput circuit 120 samples the pixel voltage may also be reducedcompared to the example embodiment illustrated in FIG. 4. Accordingly,in the example embodiment illustrated in FIG. 5, the storage time ST maybe reduced compared to the example embodiment illustrated in FIG. 4.

Referring to FIG. 5, during the storage time ST and the readout time RT,the first enable element EX1 and the second enable element EX2 maymaintain a turned-off state. The example embodiment illustrated in FIG.5 may be a high-illuminance environment in which the intensity of lightis relatively strong, and in this case, compared to the exampleembodiment illustrated in FIG. 4, the signal intensity may be increasedand noise may be weakened. Accordingly, by turning off the first enableelement EX1 in the first output circuit 110 and connecting only thefirst primary capacitor MC1 to the first switching element SW1, thesettling time required to sample the reset voltage to the first primarycapacitor MC1 may be reduced, and the operation speed of the imagesensor may be improved. Similarly, in the second output circuit 120 aswell, only the second primary capacitor MC2 is connected to the secondswitching element SW2 to shorten the settling time.

Next, referring to FIG. 6, two readout operations may be performed at afirst readout time RT1 and a second readout time RT2. In an exampleembodiment illustrated in FIG. 6, the operation of the pixel 100 duringthe exposure time EIT and the storage time ST may be similar to theexample embodiments described above with reference to FIGS. 4 and 5.During the first readout time RT1, the logic circuit of the image sensormay read the reset voltage from the first output circuit 110 through thefirst column line COL1, and may read the pixel voltage from the secondoutput circuit 120 through the second column line COL2.

Since the first output circuit 110 includes the first output drivingelement DX1 and the second output circuit 120 includes the second outputdriving element DX2, an offset component due to a difference between thefirst output driving element DX1 and the second output driving elementDX2 may be included between the voltage output from the first outputcircuit 110 and the voltage output from the second output circuit 120.For example, the offset component may occur due to a difference inthreshold voltages between the first output driving element DX1 and thesecond output driving element DX2. In the example embodiment illustratedin FIG. 6, the offset component may be removed by executing the firstreadout operation during the first readout time RT1 and the secondreadout operation during the second readout time RT2.

During the first readout time RT1, the logic circuit of the image sensormay obtain the reset voltage and the pixel voltage. During theintermediate reset time MRT after the first readout time RT1, the resetelement RX, the first switching element SW1, and the second switchingelement SW2 are turned on, and a predetermined reference voltage may becommonly input to the first output circuit 110 and the second outputcircuit 120. The first output driving element DX1 and the second outputdriving element DX2 may operate as a source-follower amplifier by areference voltage. Thereafter, the reset element RX, the first switchingelement SW1, and the second switching element SW2 are turned off, andthe logic circuit may read the reference voltage from the first andsecond output circuits 110 and 120 through the first column line COL1and the second column line COL2.

An offset component due to a difference in threshold voltages betweenthe first output driving element DX1 and the second output drivingelement DX2 may occur in both the first readout operation and the secondreadout operation. When the reset voltage, pixel voltage, referencevoltage, and offset component are considered, the firstanalog-to-digital converter connected to the first column line COL1sequentially outputs the reset voltage and the reference voltage, andthe second analog-to-digital converter connected to the second columnline COL2 may sequentially output (pixel voltage+offset component) and(reference voltage+offset component). The above example may be anexample embodiment in which an offset component based on a differencebetween the first output driving element DX1 and the second outputdriving element DX2 is reflected in the second output driving elementDX2.

For example, a first raw image signal obtained by calculating thedifference between the output of the first analog-to-digital converterand the output of the second analog-to-digital converter during thefirst readout time RT1 may be calculated as the (reset voltage-pixelvoltage-offset component). On the other hand, a second raw image signalobtained by calculating the difference between the output of the firstanalog-digital converter and the output of the second analog-digitalconverter during the second read-out time RT2 may be calculated as the(reference voltage-reference voltage-offset component). Therefore, bycalculating the difference between the first raw image signal and thesecond raw image signal, the offset component may be removed and imagedata corresponding to (reset voltage-pixel voltage) may be accuratelyobtained.

In the example embodiment illustrated in FIG. 6, the first enableelement EX1 and the second enable element EX2 may maintain a turned-onstate during the storage time ST and the read-out time RT. However,according to example embodiments, for example, in an example embodimentin which the exposure time EIT decreases due to an increase in lightintensity in an imaging environment, the first enable element EX1 andthe second enable element EX2 may also be maintained in the turned-offstate.

FIG. 7 is a schematic circuit diagram of a pixel included in an imagesensor according to an example embodiment. In the pixel 100 according toan example embodiment illustrated in FIG. 7, the pixel circuit 105 maybe the same as that in the example embodiment described above withreference to FIG. 3. Unlike the example embodiment illustrated in FIG.3, in the example embodiment illustrated in FIG. 7, the first outputcircuit 110 and the second output circuit 120 may share one enableelement EX. The enable element EX is controlled by an enable signal EN,and may be connected to the power node 101 supplying the power voltageVDD, as shown.

When the enable element EX is turned off, only the first primarycapacitor MC1 and the second primary capacitor MC2 are connected to thepixel circuit 105, and the first secondary capacitor VC1 and the secondsecondary capacitor VC2 may be separated from the pixel circuit 105. Asdescribed above, when a relatively long exposure time is required, theenable element EX may be turned on, for example, in a low-illuminanceimaging environment in which the intensity of light is weak. When arelatively short exposure time is required, the enable element EX may beturned off, for example, in a high-illuminance imaging environment inwhich the intensity of light is strong.

FIG. 8 is a schematic block diagram of an image sensor according to anexample embodiment. In an example embodiment illustrated in FIG. 8, animage sensor 1A may include a pixel array 10, a logic circuit 20, alight source 30, and the like. The configuration and operation of thepixel array 10 may be similar to that described with reference to FIG.1.

The light source 30 may operate by a control signal CNT output from thecontrol logic 24. For example, the control signal CNT may be a squarewave signal, and the light source 30 may output light in an infraredwavelength band. While the light source 30 outputs light by the controlsignal CNT, the logic circuit 20 may expose the pixels PX to light.Light output from the light source 30 and reflected by a subject may beincident on the pixels PX, and photodiodes may react to the light togenerate electrical charge.

The image sensor 1A according to the example embodiment illustrated inFIG. 8 may be applied to various fields such as a camera device for facerecognition, an autonomous vehicle, and driver monitoring of a vehicle.In addition, the logic circuit 20 may obtain a first digital pixelsignal from a first pixel voltage corresponding to electrical chargesgenerated by the photodiodes while the light source 30 is operating, andmay obtain a second digital pixel signal from a second pixel voltagecorresponding to electrical charges generated by the photodiodes whilethe light source 30 is not operating. The logic circuit 20 may generateimage data by calculating a difference between the first digital pixelsignal and the second digital pixel signal, and may remove effects ofambient light other than the light output from the light source 30.

FIG. 9 is a diagram provided to describe the operation of the imagesensor according to an example embodiment. FIG. 9 may be a diagramprovided to illustrate the operation of the image sensor 1A includingthe light source 30. Referring to FIGS. 8 and 9 together, photodiodes ofthe plurality of pixels PX included in the pixel array 10 may besimultaneously reset during a first reset time T_(RST1). For example,the row driver 21 may reset the photodiodes by turning on the resetelements included in the pixels PX to remove electrical charges from thephotodiodes.

When the photodiodes are reset, the photodiodes included in theplurality of pixels PX may be exposed to light during a first exposuretime T_(EX1) to generate electrical charge. During the first exposuretime T_(EX1), the control logic 24 may operate the light source 30 byoutputting the control signal CNT to the light source 30. During thefirst exposure time T_(EX1), the photodiodes may generate electricalcharges in response to light output from the light source 30 andreflected from the subject and ambient light other than light outputfrom the light source 30.

A first pixel voltage corresponding to the electrical charge generatedby the photodiodes during the first exposure time T_(EX1) may be sampledby a first output circuit included in each of the pixels PX. The firstexposure time T_(EX1) may include a time at which the photodiodes areexposed to light, and a time at which the first output circuit of eachof the pixels PX samples the first pixel voltage corresponding to theelectrical charge generated by the photodiodes.

During a second reset time T_(RST2) after the first exposure timeT_(EX1), the logic circuit 20 may reset the pixels PX included in thepixel array 10 again. When the pixels PX are reset to remove electricalcharges from the photodiodes, the logic circuit 20 may expose the pixelsto light again during the second exposure time T_(EX2). During thesecond exposure time T_(EX2), the light source 30 may not operate.Accordingly, during the second exposure time T_(EX2), the photodiodesmay generate electrical charges in response to ambient light. The secondpixel voltage corresponding to the electrical charge generated by thephotodiodes during the second exposure time T_(EX2) may be sampled bythe second output circuit included in each of the pixels PX.

During the readout time T_(RO), the row driver 21 may scan the pluralityof respective row lines. The readout circuit 22 may perform a readoutoperation for each of the pixels PX according to an order in which therow driver 21 scans a plurality of row lines. The readout circuit 22 mayobtain a first digital pixel signal and a second digital pixel signal bycomparing the first pixel voltage and the second pixel voltage stored ineach of the pixels PX with the ramp voltage during the readout timeT_(RO).

FIGS. 10 to 12 are views provided to illustrate the operation of animage sensor according to an example embodiment. Referring to FIGS. 10and 11, a pixel 200 of the image sensor may include a photodiode PD, apixel circuit 205, a first output circuit 210, a second output circuit220, and the like. The configuration and operation of the pixel circuit205, the first output circuit 210, and the second output circuit 220 maybe similar to those described above with reference to FIG. 3.

FIG. 10 may be a diagram for describing the operation of the pixel 200while the light source included in the image sensor is operating, andFIG. 11 is a diagram illustrating the operation of the pixel 200 whilethe light source included in the image sensor is not operating.Hereinafter, the operation of the pixel 200 will be described withreference to FIGS. 10, 11 and 12 together.

Referring to FIG. 12, in the operation of the pixel 200, first, thereset element RX and the transfer element TX may be turned on by thereset control signal RG and the transfer control signal TG, andelectrical charges of the photodiode PD and the floating diffusion nodeFD may be removed. When the electrical charge of the photodiode PD andthe floating diffusion node FD is removed and the reset operation iscompleted, the first exposure time EIT1 may start. During the firstexposure time EIT1, the photodiode PD is exposed to light to generateelectrical charge, and when the first exposure time EIT1 elapses, thetransfer element TX is turned on, and electrical charges of thephotodiode PD may move to the floating diffusion node FD.

When the transfer element TX is turned off, the first switching elementSW1 is turned on by the first switch control signal SG1 for a firstsampling time T1, and the first output circuit 210 may sample the firstpixel voltage output from the driving element DX as illustrated in FIG.10. The first pixel voltage may be a voltage corresponding to electricalcharge generated by the photodiode PD during the first exposure timeEIT1. On the other hand, while the first output circuit 210 samples thefirst pixel voltage, the bias element BX is turned on to supply a biascurrent required for the operation of the driving element DX. As anexample, the bias element BX may be turned on for a first storage timeST1 that is longer than the first sampling time T1.

Referring to FIG. 12, the light source may be operated by the controlsignal CNT during the first exposure time EIT1. Accordingly, the firstpixel voltage sampled by the first output circuit during the firstsampling time T1 may be a voltage corresponding to electrical chargegenerated by the photodiode PD by light output from the light source andambient light. Although the example embodiment in FIG. 12 illustratesthat the light source may be turned on even during the first storagetime ST1 and the first sampling time T1, unlike this, the light sourcemay only be turned on during the first exposure time EIT1.

When the first sampling time T1 and the first storage time ST1 areterminated, the reset element RX and the transfer element TX are turnedon again, and the floating diffusion node FD and the photodiode PD aremay be reset. The photodiode PD may be exposed to light during thesecond exposure time EIT2 after the reset operation to generateelectrical charge. Since the light source does not operate during thesecond exposure time EIT2, the photodiode PD may generate electricalcharge only by ambient light during the second exposure time EIT2without the influence of the light source.

When the second exposure time EIT2 elapses, the transfer element TX isturned on, the electrical charge of the photodiode PD moves to thefloating diffusion node FD, and the driving element DX may operate as asource-follower amplifier by the turned-on bias element BX. Also, duringthe second sampling time T2, the second switching element SW2 may beturned on, and the second output circuit 220 may sample the second pixelvoltage as illustrated in FIG. 11. The second pixel voltage may be avoltage corresponding to electrical charge generated by the photodiodePD only by ambient light without an influence of a light source.

When the second sampling time T2 and the second storage time ST2 elapse,the first pixel voltage and the second pixel voltage may be read duringthe first readout time RT1. During the first read-out time RT1, theread-out circuit of the image sensor may compare the first pixel voltageoutput through the first column line COL1 with the ramp voltage RMP toobtain a first digital pixel signal. In addition, the readout circuitmay obtain a second digital pixel signal by comparing the second pixelvoltage output through the second column line COL2 with the ramp voltageRMP during the first readout time RT1.

When the first readout time RT1 elapses, the reset element RX is turnedon to reset the floating diffusion node FD. In this case, the firstswitching element SW1 and the second switching element SW2 together withthe reset element RX are turned on, and thus, the reset voltage may besampled to capacitors MC1 and VC1 of the first output circuit 110 andcapacitors MC2 and VC2 of the second output circuit 120. The readoutcircuit may obtain a digital reset signal by comparing the reset voltageoutput from the first output circuit 210 and the second output circuit220 with the ramp voltage RMP during the second readout time RT2.

The readout circuit may calculate a difference between the digital resetsignal and the first digital pixel signal to obtain a first digitalsignal, and may calculate a difference between the digital reset signaland the second digital pixel signal to obtain a second digital signal.The first pixel voltage reflects the light output from the light sourceand the influence of the ambient light, whereas the second pixel voltagereflects only the effect of the ambient light so that the differencebetween the first digital signal and the second digital signal iscalculated to eliminate the influence of ambient light. Accordingly, theimage sensor may acquire accurate image data generated by light outputfrom the light source.

On the other hand, referring to FIG. 12, the first enable element EX1and the second enable element EX2 may maintain a turned-off state. Bymaintaining the first enable element EX1 and the second enable elementEX2 in a turned-off state, the capacity of the first output circuit 210and the second output circuit 220 may be reduced, and a settling timerequired for the sampling operation may be reduced. Accordingly, despitethe two exposure times EIT1 and EIT2, a function of removing ambientlight may be implemented while significantly inhibiting a decrease inthe operation speed of the image sensor.

FIG. 13 is a diagram provided to describe the operation of an imagesensor according to an example embodiment. In the example embodimentillustrated in FIG. 13, the image sensor may operate in a global shuttermethod. During the first reset time T_(RST1) the reset element and thetransfer element included in the pixels are turned on to removeelectrical charges from the photodiode and the floating diffusion nodein each of the pixels. Accordingly, the voltage of the floatingdiffusion node may be completely reset.

During the first exposure time T_(EX1), the pixels may be simultaneouslyexposed to light, and photodiodes may react to the light to generateelectrical charge. The first pixel voltage corresponding to theelectrical charge generated by the photodiodes during the first exposuretime T_(EX1) may be sampled by the first output circuit included in eachof the pixels. As an example, electrical charges generated byphotodiodes during the first exposure time T_(EX1) may be stored in acapacitor included in the first output circuit.

When the first exposure time T_(EX1) elapses, the reset element and thetransfer element included in the pixels are turned on again to removeelectrical charges from the photodiode and the floating diffusion nodein each of the pixels. For example, electrical charges from thephotodiode and the floating diffusion node may be removed during thesecond reset time T_(RST2).

During the second exposure time T_(EX2), the operation of the pixels maybe similar to the operation of the first exposure time T_(EX1), and thesecond exposure time T_(EX2) may be shorter than the first exposure timeT_(EX1). The second pixel voltage corresponding to the electrical chargegenerated by the pixels during the second exposure time T_(EX2) may besampled by the second output circuit of each of the pixels. Due to adifference between the first exposure time T_(EX1) and the secondexposure time T_(EX2), the first pixel voltage and the second pixelvoltage may be different from each other.

For example, the electrical charge generated by the photodiodes duringthe first exposure time T_(EX1) may be greater than the electricalcharge generated by the photodiodes during the second exposure timeT_(EX2). The image sensor may read a first pixel voltage and a secondpixel voltage from the respective pixels during the readout time T_(RO),and may generate image data using the first pixel voltage and the secondpixel voltage. For example, by generating one image data using the firstpixel voltage and the second pixel voltage, the dynamic range of theimage data may be improved.

The image sensor may also set conversion gains of pixels differently atthe first exposure time T_(EX1) and the second exposure time T_(EX2),respectively. For example, a first conversion gain of each of the pixelsduring the first exposure time T_(EX1) may be smaller than a secondconversion gain of each of the pixels during the second exposure timeT_(EX2).

In the example embodiment illustrated in FIG. 13, since the first outputcircuit of each of the pixels samples the first pixel voltage, and thesecond output circuit samples the second pixel voltage, the readoutcircuit of the image sensor during the readout time T_(RO) may firstread the first pixel voltage and the second pixel voltage and then mayread the reset voltage later. To read the reset voltage, the first pixelvoltage and the second pixel voltage may be read, and then, the resetoperation may be executed.

FIGS. 14 to 16 are diagrams provided to illustrate the operation of theimage sensor according to an example embodiment. Referring to FIGS. 14and 15, a pixel 300 of an image sensor may include a photodiode PD, apixel circuit 305, a first output circuit 310, a second output circuit320, and the like. The configuration and operation of the first outputcircuit 310 and the second output circuit 320 may be similar to thosedescribed with reference to FIG. 3.

On the other hand, referring to FIGS. 14 and 15, the pixel circuit 305may further include a conversion gain control element DCX in addition tothe transfer element TX, the reset element RX, and the driving elementDX. The conversion gain control element DCX is connected between thereset element RX and the floating diffusion node FD, and may becontrolled by a conversion gain control signal DCG. For example, whenthe conversion gain control element DCX is turned on, the capacity ofthe floating diffusion node FD may increase and the conversion gain ofthe pixel circuit 305 may decrease. Conversely, when the conversion gaincontrol element DCX is turned off, the capacity of the floatingdiffusion node FD may decrease and the conversion gain of the pixelcircuit 305 may increase.

FIG. 14 may be a diagram for describing an operation of the pixel 300during a relatively long exposure time, and FIG. 15 may be a diagram fordescribing an operation of the pixel 300 during a relatively shortexposure time. Hereinafter, the operation of the pixel 300 will bedescribed with reference to FIG. 16.

Referring to FIG. 16, in the operation of the pixel 300, first, thereset element RX and the transfer element TX may be turned on by a resetcontrol signal RG and a transfer control signal TG, and electricalcharges of the photodiode PD and the floating diffusion node FD may beremoved. When the reset operation is completed, the first exposure timeEIT1 may start. During the first exposure time EIT1, the photodiode PDis exposed to light to generate electrical charge, and when the firstexposure time EIT1 elapses, the transfer element TX is turned on andelectrical charge of the photodiode PD may move to the floatingdiffusion node FD. When the first exposure time EIT1 starts, theconversion gain control element DCX is turned on so that the conversiongain of the pixel circuit 305 may decrease.

When the first exposure time EIT1 elapses, the transfer element TX maybe turned off, and the first switching element SW1 may be turned on bythe first switch control signal SG1 during the first sampling time T1.During the first sampling time T1, as illustrated in FIG. 14, the firstoutput circuit 310 may sample the first pixel voltage output from thedriving element DX. The first pixel voltage may be a voltagecorresponding to electrical charge generated by the photodiode PD duringthe first exposure time EIT1. During the first sampling time T1, thefirst enable element EX1 is turned on so that the first secondarycapacitor VC1 may be connected to the first switching element SW1.

On the other hand, while the first output circuit 310 samples the firstpixel voltage, the bias element BX is turned on to supply a bias currentrequired for the operation of the driving element DX. As an example, thebias element BX may be turned on for a first storage time ST1 that islonger than the first sampling time T1. At least a portion of the firststorage time ST1 may overlap the first exposure time EIT1.

When the first sampling time T1 and the first storage time ST1 arefinished, the reset element RX and the transfer element TX are turned onagain, and the floating diffusion node FD and the photodiode PD are maybe reset. After the reset operation, the photodiode PD may be exposed tolight during the second exposure time EIT2 to generate electricalcharge. The second exposure time EIT2 may be shorter than the firstexposure time EIT1, and the conversion gain control element DCX may notbe turned on during the second exposure time EIT2.

When the second exposure time EIT2 elapses, the transfer element TX isturned on, the electrical charge of the photodiode PD moves to thefloating diffusion node FD, and the driving element DX may operate as asource-follower amplifier by the turned-on bias element BX. Also, thesecond switching element SW2 is turned on during the second samplingtime T2, and the second output circuit 120 may sample the second pixelvoltage as illustrated in FIG. 11. The second pixel voltage may be avoltage corresponding to the electrical charge generated by thephotodiode PD during THE second exposure time EIT2 shorter than thefirst exposure time EIT1.

When the second sampling time T2 and the second storage time ST2 elapse,the readout circuit of the image sensor may read the first pixel voltageand the second pixel voltage during the first readout time RT1. Duringthe first readout time RT1, the readout circuit of the image sensorcompares each of the first pixel voltage and the second pixel voltagewith the ramp voltage RMP to obtain a first digital pixel signal and asecond digital pixel signal.

When the first readout time RT1 elapses, the reset element RX is turnedon to reset the floating diffusion node FD. At this time, the firstswitching element SW1 and the second switching element SW2 together withthe reset element RX may be turned on so that the reset voltage issampled to the first output circuit 310 and the second output circuit320. The readout circuit may obtain a digital reset signal by comparingthe reset voltages output from the first output circuit 310 and thesecond output circuit 320 with the ramp voltage RMP during the secondreadout time RT2.

In the example embodiment described with reference to FIGS. 14 to 16,the logic circuit of the image sensor may set the first exposure timeEIT1 and the second exposure time EIT2 shorter than the first exposuretime EIT1, during one frame period. The logic circuit may connect thefirst output circuit 310 to the pixel circuit 305, between the firstexposure time EIT1 and the second exposure time EIT2, and may connectthe second output circuit 320 to the pixel circuit 305 after the secondexposure time EIT2. Accordingly, the logic circuit may acquire the firstdigital pixel signal, the second digital pixel signal, and the digitalreset signal during one frame period.

The logic circuit of the image sensor may calculate a difference betweena digital reset signal and a first digital pixel signal to obtain afirst digital signal, and may calculate a difference between the digitalreset signal and a second digital pixel signal to obtain a seconddigital signal. The first digital signal may correspond to a relativelylong first exposure time EIT1, and the second digital signal maycorrespond to a relatively short second exposure time EIT2. Further, thefirst digital signal may be a signal generated under a relatively lowerconversion gain condition than the second digital signal. By generatingimage data using the first digital signal and the second digital signal,the dynamic range of the image data may be improved.

FIG. 17 is a diagram illustrating a portion of pixels included in animage sensor according to an example embodiment. Referring to FIG. 17,an image sensor 400 may include a semiconductor substrate 401, aphotodiode 403 and elements 410 formed in the semiconductor substrate401, and metal wirings 411 and 412 connected to the elements 410, aninsulating layer 420 filling the elements 410 and the metal wirings 411and 412, and the like. The semiconductor substrate 401 may be asubstrate including a semiconductor material such as silicon, and thephotodiode 403 may be formed in the semiconductor substrate 401. Forexample, the photodiode 403 may be formed by a process of implantingimpurities into the semiconductor substrate 401, and the photodiode 403may be connected to at least one of the elements 410.

A light transmitting layer 405 and a microlens 407 may be formed on onesurface of the semiconductor substrate 401. The light transmitting layer405 may include a color filter that selectively transmits light of aspecific wavelength band. According to example embodiments, in at leastsome of pixels disposed in different positions in the image sensor 400,the microlenses 407 may be formed to have different curvature radii.Accordingly, in at least some of the pixels, the upper surfaces of themicrolenses 407 may be positioned at different heights.

The elements 410 may provide a pixel circuit, a first output circuit,and a second output circuit. For example, the elements 410 may include atransfer element, a reset element, driving elements, switching elements,selection elements, enable elements, and the like. The elements 410 areconnected to the photodiode 403 and may also be connected to capacitors413 buried in the insulating layer 420 through metal wirings 411 and412. As an example, the capacitors 413 may be connected to a switchingelement and an enable element among the elements 410, and the primarycapacitors among the capacitors 413 may be connected to wiring, whichsupplies a power voltage among the metal wirings 411 and 412.

The manufacturing process of the capacitors 413 may include a process offorming a dielectric film. To improve the leakage characteristics of thecapacitors 143, a process of forming a dielectric film may be performedat a relatively high temperature. In an example embodiment, lowerwirings 411 formed before formation of the capacitors 413 may be formedof tungsten so that the dielectric film may be formed at a hightemperature. On the other hand, upper wirings 412 formed later than theformation of the capacitors 413 may be formed of copper or the like,which is only an example embodiment, and thus, the lower wirings 411 andthe upper wirings 412 may be formed of the same material.

FIGS. 18 and 19 are diagrams schematically illustrating an image sensoraccording to an example embodiment. First, referring to FIG. 18, animage sensor 500 according to an example embodiment may include a firstlayer 510 and a second layer 520. The first layer 510 and the secondlayer 520 may be stacked in a vertical direction. The first layer 510may include a pixel array 511, and the second layer 520 may includelogic circuits 521 and 522. The pixel array 511 includes a plurality ofpixels, and the plurality of pixels may be connected to the logiccircuit 521 through a plurality of row lines and a plurality of columnlines. In the example embodiment illustrated in FIG. 18, each of thepixels disposed in the pixel array 511 in the first layer 510 mayinclude a pixel circuit, a first output circuit, and a second outputcircuit. Accordingly, each of the pixels may have a structure similar tothat of the example embodiment described above with reference to FIG.17.

The logic circuits 521 and 522 may include a first logic circuit 521 anda second logic circuit 522. The first logic circuit 521 may include arow driver, a readout circuit, a column driver, and control logicnecessary for driving the pixel array 511. The second logic circuit 522may include a power circuit, an input/output interface, an image signalprocessor, and the like. The area and arrangement form occupied by therespective first and second logic circuits 521 and 522 may be variouslymodified.

Next, referring to FIG. 19, an image sensor 600 may include a firstlayer 610, a second layer 620, and a third layer 630 that aresequentially stacked. The first layer 610, the second layer 620, and thethird layer 630 may be formed on different semiconductor substrates, tobe stacked on each other. The third layer 630 includes a first logiccircuit 631 and a second logic circuit 632, and the configurations ofthe first logic circuit 631 and the second logic circuit 632 may besimilar to those described with reference to FIG. 18.

The first layer 610 may include a first pixel array 611, and the secondlayer 620 may include a second pixel array 621. The first pixel array611 and the second pixel array 621 may be connected to each other toprovide a plurality of pixels. As an example, each of the pixels mayinclude a photodiode, a pixel circuit, a first output circuit, a secondoutput circuit, and the like, as in the other embodiments describedabove, and the photodiode and the pixel circuit may be disposed in thefirst pixel array 611, and the first output circuit and the secondoutput circuit may be disposed in the second pixel array 621. The pixelcircuit of the first pixel array 611 may be connected to the firstoutput circuit and the second output circuit of the second pixel array621 by a method such as Cu—Cu bonding or the like.

A process of forming capacitors included in the first output circuit andthe second output circuit may be performed at a relatively hightemperature to improve leakage characteristics of the capacitors.Therefore, in a case in which the pixel circuit, the first outputcircuit, and the second output circuit are all formed in one layer, thepixel circuit, the wiring patterns directly connected to the firstoutput circuit, the second output circuit and the pixel circuit may berequired to be formed of tungsten.

Meanwhile, in the example embodiment illustrated in FIG. 19, since theprocesses of the pixel circuit, the first output circuit, and the secondoutput circuit are separated from each other, wiring patterns connectedto the reset element, the transfer element, the driving element, etc. ofthe pixel circuit may be formed of copper or the like, which has amelting point lower than that of tungsten, but has excellent reflectanceand resistance properties. Since the wiring patterns formed of copperhaving relatively high reflectivity are disposed below the photodiodeand the pixel circuit, photoelectric conversion efficiency of the imagesensor may be improved. In addition, according to example embodiments,all elements included in the pixel circuit, the first output circuit,and the second output circuit may be formed in the first layer 610, andseparately, capacitors may be formed in the second layer 620. In thiscase, most of the metal wirings for connecting the elements andcapacitors in the pixel circuit, the first output circuit, and thesecond output circuit may be formed of copper, and thus, resistancecharacteristics may be improved, which will be described below in moredetail with reference to FIGS. 20 and 21.

FIGS. 20 to 22 are diagrams illustrating some of pixels included in animage sensor according to an example embodiment. First, referring toFIG. 20, an image sensor 700 according to an example embodiment mayinclude a first layer L1 and a second layer L2. According to exampleembodiments, a third layer on which logic circuits are formed may beadded on the second layer L2. Alternatively, logic circuits may also beformed together with pixels in the first layer L1 or the second layerL2.

In the example embodiment illustrated in FIG. 20, the first layer L1 mayinclude a photodiode 703 and a pixel circuit among constituent elementsof each of the pixels. Referring to the first layer L1, a photodiode 703is formed in a first semiconductor substrate 701, and a lighttransmitting layer 705 and a microlens 707 may be formed on one surfaceof the first semiconductor substrate 701. In addition, elements 710included in the pixel circuit are formed on the first semiconductorsubstrate 701, and the elements 710 and metal wirings 711 connected tothe elements 710 may be buried in an insulating layer 720. The elements710 may provide a transfer element, a reset element, a driving element,a conversion gain control element, a floating diffusion node, and thelike.

The second layer L2 is disposed on the first layer L1 and may include afirst output circuit and a second output circuit among constituentelements of each of the pixels. The second layer L2 may include elements730 formed on a second semiconductor substrate 702 and included in thefirst output circuit or the second output circuit. The elements 730 areconnected to each other by metal wirings 741, and the elements 730 andthe metal wirings 741 may be buried in an insulating layer 750. At leasta portion of the metal wirings 741 of the second layer L2 may beconnected to at least a portion of the metal wirings 711 of the firstlayer L1 through a bonding pattern 760. In detail, the second layer L2may be connected to the first layer L1 by the Cu—Cu bonding method orthe like. For example, the bonding pattern 760 may be a node in which afirst switching element and a second switching element included in thefirst and second output circuits, respectively, are connected to thedriving element of the pixel circuit.

The second layer L2 may include capacitors 755 buried in the insulatinglayer 750. The capacitors 755 are components included in the first andsecond output circuits; the capacitors 755 can be advantageously used tosample a pixel voltage and/or a reset voltage generated by the pixelcircuit of the first layer L1. For example, the capacitors 755 mayinclude a primary capacitor and a secondary capacitor, the primarycapacitor may be connected to a power node and a switching element, andthe secondary capacitor may be connected to an enable element and aswitching element.

Next, referring to FIG. 21, an image sensor 800 according to an exampleembodiment may include a first layer L1 and a second layer L2.Hereinafter, descriptions of components that are similar to those ofFIG. 20 or that may be understood with reference to FIG. 20 will beomitted. In the example embodiment illustrated in FIG. 21, onlycapacitors 835 may be formed in the second layer L2, and elements 810for providing a pixel circuit, a first output circuit, and a secondoutput circuit may all be formed in the first layer L1 together with thephotodiode 803. For example, photodiodes 803 and elements 810 includedin the pixel circuit and the first and second output circuits are formedin a first semiconductor substrate 801, and metal wirings 811 and aninsulating layer 820 may be formed. In this case, a bonding pattern 840for connecting the capacitors 835 of the second layer L2 and the metalwirings 811 may be formed in the first layer L1.

In addition, capacitors 835, metal wirings 831, and an insulating layer830 are formed on a second semiconductor substrate different from thefirst semiconductor substrate 801, and the bonding patterns 840 areconnected to each other by Cu—Cu bonding, such that the first layer L1and the second layer L2 may be attached to each other. When the firstlayer L1 and the second layer L2 are attached to each other, a partialregion of the first semiconductor substrate 801 is removed from thefirst layer L1 by a polishing process, etc., and a light transmittinglayer 805 and a microlens 807 may be formed. Optionally, the secondsemiconductor substrate for the formation of the capacitors 835 may beremoved by a polishing process or the like, and the insulating layer 830may be exposed.

In the example embodiment illustrated in FIG. 21, a logic circuit fordriving pixels and generating image data may be disposed in at least oneof the first layer L1 and the second layer L2. When at least a portionof the logic circuit is disposed in the second layer L2, the secondsemiconductor substrate for forming the second layer L2 may not beremoved by a polishing process or the like.

Also, according to example embodiments, the logic circuit may beprovided by a third layer L3 disposed on the second layer L2. Referringto FIG. 22, a second semiconductor substrate for forming a second layerL2 of an image sensor 900 may be completely removed by a polishingprocess, or the like, and a third layer L3 may be disposed on the secondlayer L2. The third layer L3 may include a third semiconductor substrate902, elements 950 providing a logic circuit, metal wirings 951, aninsulating layer 960, and the like. In an example embodiment, a portionof the metal wirings 951 of the third layer L3 may penetrate through theinsulating layer 930 of the second layer L2, and may be connected to atleast one of the metal wirings 911 of the first layer L1 by a verticalvia disposed on outside of the pixels.

FIGS. 23 and 24 are diagrams schematically illustrating an electronicdevice including an image sensor according to an example embodiment.Referring to FIG. 23, an electronic device 1000 may include a cameramodule group 1100, an application processor 1200, a PMIC 1300, and anexternal memory 1400. The camera module group 1100 may include aplurality of camera modules 1100 a, 1100 b, and 1100 c. Although thedrawing illustrates an example embodiment in which three camera modules1100 a, 1100 b, and 1100 c are disposed, the example embodiments are notlimited thereto. In some embodiments, the camera module group 1100 maybe modified to include only two camera modules. In addition, in someembodiments, the camera module group 1100 may be modified andimplemented to include n (where n is a natural number of 4 or more)camera modules. In addition, in an example embodiment, at least one ofthe plurality of camera modules 1100 a, 1100 b, and 1100 c included inthe camera module group 1100 may include the image sensor according toone of the example embodiments described with reference to FIGS. 1 to 22above.

Hereinafter, a detailed configuration of a camera module 1100 b will bedescribed in more detail with reference to FIG. 24, but the followingdescription may be equally applied to other camera modules 1100 a and1100 b according to example embodiments. Referring to FIG. 24, thecamera module 1100 b includes a prism 1105, an optical path foldingelement (hereinafter referred to as “OPFE”) 1110, an actuator 1130, animage sensing device 1140, and a storage unit 1150.

The prism 1105 may include a reflective surface 1107 of a lightreflecting material to change the path of light L incident from theoutside thereof. In some embodiments, the prism 1105 may change the pathof the light L incident in a first direction X into a second direction Yperpendicular to the first direction X. In addition, the prism 1105rotates the reflective surface 1107 of the light reflecting material inan A direction around a central axis 1106, or rotates the central axis1106 in a B direction, to change the path of the light L incident in thefirst direction X to the second direction Y that is a verticaldirection. In this case, the OPFE 1110 may also move in a thirddirection Z perpendicular to the first direction X and the seconddirection Y.

In some embodiments, as illustrated, a maximum rotation angle of theprism 1105 in the A direction may be equal to or less than 15 degrees inthe plus (+) A direction, and may be greater than 15 degrees in theminus (−) A direction, but the embodiments are not limited thereto. Insome embodiments, the prism 1105 may move between 20 degrees in a plus(+) or minus (−) B direction, or between 10 degrees and 20 degrees, orbetween 15 degrees and 20 degrees. In this case, the angle of movementmay move at the same angle in the plus (+) or minus (−) B direction, ormay move to an almost similar angle to about 1 degree.

In some embodiments, the prism 1105 may move the reflective surface 1106of the light reflecting material in the third direction (e.g., the Zdirection) parallel to the extending direction of the central axis 1106.

The OPFE 1110 may include, for example, an optical lens comprised of m(where m is a natural number) groups. M lenses may move in the seconddirection Y to change the optical zoom ratio of the camera module 1100b. For example, when the basic optical zoom ratio of the camera module1100 b is Z, in the case of moving m optical lenses included in the OPFE1110, the optical zoom ratio of the camera module 1100 b may be changedto an optical zoom ratio of 3Z, 5Z or more than 5Z.

The actuator 1130 may move the OPFE 1110 or an optical lens,(hereinafter, referred to as an optical lens), to a specific position.For example, the actuator 1130 may adjust the position of the opticallens so that an image sensor 1142 is positioned at the focal length ofthe optical lens for accurate sensing.

The image sensing device 1140 may include the image sensor 1142, acontrol logic 1144, and a memory 1146. The image sensor 1142 may sensean image of a sensing target using light L provided through an opticallens. The control logic 1144 may control the overall operation of thecamera module 1100 b. For example, the control logic 1144 may controlthe operation of the camera module 1100 b by a control signal providedthrough a control signal line CSLb.

The memory 1146 may store information, such as calibration data 1147,required for the operation of the camera module 1100 b. The calibrationdata 1147 may include information necessary for the camera module 1100 bto generate image data using the light L provided from the outsidethereof. The calibration data 1147 may include, for example, informationon a degree of rotation described above, information on a focal length,information on an optical axis, and the like. When the camera module1100 b is implemented in the form of a multi-state camera of which afocal length is changed based on the position of the optical lens, thecalibration data 1147 may include the focal length values for respectivepositions (or per state) of the optical lens, and information related toautofocusing.

The storage unit 1150 may store image data sensed through the imagesensor 1142. The storage unit 1150 may be disposed on outside of theimage sensing device 1140, and may be implemented in a stacked form witha sensor chip constituting the image sensing device 1140. In someembodiments, the storage unit 1150 may be implemented as an ElectricallyErasable Programmable Read-Only Memory (EEPROM), but the embodiments arenot limited thereto.

Referring to FIGS. 23 and 24 together, in some embodiments, each of theplurality of camera modules 1100 a, 1100 b, and 1100 c may include theactuator 1130. Accordingly, each of the plurality of camera modules 1100a, 1100 b, and 1100 c may include calibration data 1147 that are thesame or different from each other based on the operation of the actuator1130 included therein. In some further embodiments, one camera module(for example, 1100 b) among the plurality of camera modules 1100 a, 1100b and 1100 c is a folded lens-type camera module including the prism1105 and the OPFE 1110 described above, and the remaining camera modules(e.g., 1100 a and 1100 c) may be vertical-type camera modules that donot include the prism 1105 and the OPFE 1110, but the embodiments arelimited thereto.

In additional embodiments, one camera module (e.g., 1100 c) among theplurality of camera modules 1100 a, 1100 b and 1100 c may be, forexample, a vertical-type of depth camera for extracting depthinformation using Infrared Ray (IR). In this case, an applicationprocessor 1200 merges the image data provided from the depth camera withthe image data provided from another camera module (for example, 1100 aor 1100 b) to generate a 3D depth image.

In still further embodiments, at least two camera modules (e.g., 1100 aand 1100 b) among the plurality of camera modules 1100 a, 1100 b, and1100 c may have different fields of view. In this case, for example, theoptical lenses of at least two camera modules (e.g., 1100 a and 1100 b)among the plurality of camera modules 1100 a, 1100 b and 1100 c may bedifferent from each other, but the configuration is not limited thereto.

Also, in some embodiments, fields of view of the plurality of cameramodules 1100 a, 1100 b, and 1100 c may be different. In this case,optical lenses included in each of the plurality of camera modules 1100a, 1100 b, and 1100 c may also be different from each other, but theconfiguration is not limited thereto. In addition, the plurality ofcamera modules 1100 a, 1100 b, and 1100 c may be physically separatedfrom each other and disposed. For example, the sensing area of one imagesensor 1142 is not divided and used by the plurality of camera modules1100 a, 1100 b and 1100 c, but an independent image sensor 1142 may bedisposed inside each of the plurality of camera modules 1100 a, 1100 b,and 1100 c.

Referring back to FIG. 23, the application processor 1200 may include animage processing device 1210, a memory controller 1220, and an internalmemory 1230. The application processor 1200 may be implementedseparately from the plurality of camera modules 1100 a, 1100 b, and 1100c. For example, the application processor 1200 and the plurality ofcamera modules 1100 a, 1100 b, and 1100 c may be implemented by beingseparated from each other as separate semiconductor chips.

The image processing device 1210 may include a plurality of sub-imageprocessors 1212 a, 1212 b, and 1212 c, an image generator 1214, and acamera module controller 1216. The image processing device 1210 mayinclude the plurality of sub-image processors 1212 a, 1212 b, and 1212 ccorresponding to the number of the plurality of camera modules 1100 a,1100 b and 1100 c.

Image data generated from the camera modules 1100 a, 1100 b and 1100 c,respectively, may be provided to corresponding sub-image processors 1212a, 1212 b and 1212 c through image signal lines ISLa, ISLb and ISLcseparated from each other. For example, the image data generated fromthe camera module 1100 a may be provided to the sub-image processor 1212a through the image signal line ISLa, the image data generated from thecamera module 1100 b may be provided to the sub-image processor 1212 bthrough the image signal line ISLb, and the image data generated fromthe camera module 1100 c may be provided to the sub-image processor 1212c through the image signal line ISLc. Such image data transmission maybe performed using, for example, a camera serial interface (CSI) basedon a Mobile Industry Processor Interface (MIPI), but the embodiments arenot limited thereto.

On the other hand, in some embodiments, one sub-image processor may bedisposed to correspond to a plurality of camera modules. For example,the sub image processor 1212 a and the sub image processor 1212 c arenot implemented separately from each other as illustrated, but areimplemented by being integrated into one sub image processor, and theimage data provided from the camera module 1100 a and the camera module1100 c may be selected through a selection element (e.g., a multiplexer)or the like, and then, may be provided to an integrated sub-imageprocessor.

The image data provided to the respective sub-image processors 1212 a,1212 b, and 1212 c may be provided to the image generator 1214. Theimage generator 1214 may generate an output image using image dataprovided from the respective sub-image processors 1212 a, 1212 b and1212 c depending on image generating information or mode signal.Specifically, the image generator 1214 merges at least some of the imagedata generated from the camera modules 1100 a, 1100 b, and 1100 c havingdifferent fields of view depending on the image generation informationor mode signal to generate an output image. Also, the image generator1214 may generate an output image by selecting any one of image datagenerated from the camera modules 1100 a, 1100 b, and 1100 c havingdifferent fields of view depending on image generation information or amode signal.

In some embodiments, the image generation information may include a zoomsignal or zoom factor. Further, in some embodiments, the mode signal maybe, for example, a signal based on a mode selected from a user. And,when the image generation information is a zoom signal (zoom factor),and the camera modules 1100 a, 1100 b and 1100 c have different fieldsof view, the image generator 1214 may operate differently depending onthe type of zoom signal. For example, when the zoom signal is a firstsignal; after merging the image data output from the camera module 1100a and the image data output from the camera module 1100 c, the outputimage may be generated using the merged image signal, and image dataoutput from the camera module 1100 b not used for merging. If the zoomsignal is a second signal different from the first signal, the imagegenerator 1214 does not perform such image data merging, and may selectany one of the image data output from the respective camera modules 1100a, 1100 b and 1100 c, to create an output image. However, embodimentsare not limited thereto, and a method of processing image data may bemodified and implemented as needed.

In some embodiments, the image generator 1214 receives a plurality ofimage data having different exposure times from at least one of theplurality of sub-image processors 1212 a, 1212 b and 1212 c, andperforms high dynamic range (HDR) processing for the plurality of imagedata, thereby generating merged image data having an increased dynamicrange.

The camera module controller 1216 may provide a control signal to therespective camera modules 1100 a, 1100 b and 1100 c. The control signalgenerated from the camera module controller 1216 may be provided to thecorresponding camera modules 1100 a, 1100 b and 1100 c through controlsignal lines CSLa, CSLb and CSLc separated from each other.

Any one of the plurality of camera modules 1100 a, 1100 b and 1100 c isdesignated as a master camera (e.g., 1100 b) depending on a mode signalor image generation information including a zoom signal, and theremaining camera modules, for example, 1100 a and 1100 c, may bedesignated as slave cameras. Such information may be included in thecontrol signal and may be provided to the corresponding camera modules1100 a, 1100 b and 1100 c through the control signal lines CSLa, CSLb,and CSLc which are separated from each other.

Camera modules operating as masters and slaves may be changed dependingon a zoom factor or an operation mode signal. For example, when thefield of view of the camera module 1100 a is wider than a field of viewof the camera module 1100 b and represents a zoom ratio having arelatively low zoom factor, the camera module 1100 b may operate as amaster, and the camera module 1100 a is a slave. Conversely, when thezoom factor indicates a high zoom ratio, the camera module 1100 a mayoperate as a master and the camera module 1100 b may operate as a slave.

In some embodiments, a control signal provided from the camera modulecontroller 1216 to each of the camera modules 1100 a, 1100 b, and 1100 cmay include a sync enable signal. For example, when the camera module1100 b is a master camera and the camera modules 1100 a and 1100 c areslave cameras, the camera module controller 1216 may transmit a syncenable signal to the camera module 1100 b. The camera module 1100 bhaving received such a sync enable signal generates a sync signal basedon the received sync enable signal, and may transmit the generated syncsignal to the camera modules 1100 a and 1100 c via a sync signal lineSSL. The camera module 1100 b and the camera modules 1100 a and 1100 cmay be synchronized with the sync signal to transmit image data to theapplication processor 1200.

In some embodiments, a control signal provided from the camera modulecontroller 1216 to the plurality of camera modules 1100 a, 1100 b and1100 c may include mode information according to the mode signal. Basedon this mode information, the plurality of camera modules 1100 a, 1100b, and 1100 c may operate in a first operation mode and a secondoperation mode in relation to the sensing speed.

In the first operation mode, the plurality of camera modules 1100 a,1100 b and 1100 c may generate an image signal at a first rate (e.g.,generate an image signal at a first frame rate), may encode thegenerated image signal at a second rate higher than the first rate(e.g., encode an image signal having a second frame rate higher than thefirst frame rate), and may transmit the encoded image signal to theapplication processor 1200. In this case, the second rate may be 30times or less of the first rate.

The application processor 1200 stores the received image signal, forexample, the encoded image signal, in the internal memory 1230 providedtherein, and the external memory 1400 provided on the outside of theapplication processor 1200, and then, reads the encoded image signalfrom the internal memory 1230 or the external memory 1400 and decode thesignal, and may display image data generated based on the decoded imagesignal. For example, a corresponding subprocessor among the plurality ofsubprocessors 1212 a, 1212 b and 1212 c of the image processing device1210 may perform decoding, but may also perform image processing on thedecoded image signal.

The plurality of camera modules 1100 a, 1100 b, and 1100 c may generatean image signal at a third rate lower than the first rate in the secondoperation mode (e.g., generate an image signal having a third frame ratelower than the first frame rate), and may transmit the image signal tothe application processor 1200. The image signal provided to theapplication processor 1200 may be an unencoded signal. The applicationprocessor 1200 may perform image processing on the received image signalor may store the image signal in the internal memory 1230 or theexternal memory 1400.

The PMIC 1300 may supply power, such as a power voltage, to theplurality of respective camera modules 1100 a, 1100 b and 1100 c. Forexample, under the control of the application processor 1200, the PMIC1300 supplies first power to the camera module 1100 a through a powersignal line PSLa, supplies second power to the camera module 1100 bthrough a power signal line PSLb, and supplies third power to the cameramodule 1100 c through a power signal line PSLc.

The PMIC 1300 may generate power corresponding to each of the pluralityof camera modules 1100 a, 1100 b, and 1100 c in response to a powercontrol signal PCON from the application processor 1200, and may alsoadjust the power level. The power control signal PCON may include apower adjustment signal for each operation mode of the plurality ofcamera modules 1100 a, 1100 b, and 1100 c. For example, the operationmode may include a low power mode, and in this case, the power controlsignal PCON may include information on a camera module operating in alow power mode and a set power level. Levels of powers provided to theplurality of respective camera modules 1100 a, 1100 b and 1100 c may bethe same or different from each other. Also, the level of power may bedynamically changed.

As set forth above, according to example embodiments, pixels aresimultaneously exposed to light during an exposure time, and electricalcharges generated during the exposure time may be stored in capacitorsof each of the pixels. By adjusting the capacity of capacitors dependingon the shooting environment such as the intensity of light incident onan image sensor or the intensity of the infrared light source operatingin conjunction with the image sensor, the intensity of ambient light,and the like, noise characteristics and an operation speed of the imagesensor and the quality of a resulting image output by the image sensormay be improved.

While example embodiments have been illustrated and described above, itwill be apparent to those skilled in the art that modifications andvariations could be made without departing from the scope of the presentinventive concept as defined by the appended claims.

1. An image sensor, comprising: a plurality of pixels, which respectively comprise: a photodiode configured to generate electrical charges in response to light incident the image sensor; a pixel circuit including a transfer element, which is electrically connected between the photodiode and a floating diffusion node that accumulates the electrical charges, and a driving element, which is electrically connected to the floating diffusion node; a first output circuit electrically connected between a first column line and the pixel circuit, said first output circuit comprising: a first switching element electrically connected to an output terminal of the driving element, a first primary capacitor electrically connected to the first switching element, a first secondary capacitor electrically connected to or disconnected from the first switching element based on an on/off switching state of a first enable element, and a first selection element electrically connected between the first switching element and the first column line; and a second output circuit electrically connected between a second column line and the pixel circuit, said second output circuit comprising: a second switching element electrically connected to the output terminal of the driving element, a second primary capacitor electrically connected to the second switching element, a second secondary capacitor electrically connected to or disconnected from the second switching element based on an on/off switching state of a second enable element, and a second selection element electrically connected between the second switching element and the second column line.
 2. The image sensor of claim 1, wherein a capacity of the first primary capacitor is smaller than a capacity of the first secondary capacitor, and a capacity of the second primary capacitor is smaller than a capacity of the second secondary capacitor.
 3. The image sensor of claim 1, further comprising a first analog-to-digital converter electrically coupled to the first column line, and a second analog-to-digital converter electrically coupled to the second column line.
 4. The image sensor of claim 1, wherein the pixel circuit further includes a reset element electrically connected between a power supply node and the floating diffusion node, and a bias element which is configured to supply a bias current to the driving element.
 5. The image sensor of claim 1, wherein the first output circuit further includes a first output driving element electrically connected between the first switching element and the first selection element; and wherein the second output circuit further includes a second output driving element electrically connected between the second switching element and the second selection element.
 6. The image sensor of claim 1, further comprising: a logic circuit configured to: (i) drive the plurality of pixels to thereby obtain image data therefrom, and (ii) simultaneously expose the plurality of pixels to light during an exposure time, obtain a reset voltage through the first column line, and obtain a pixel voltage through the second column line.
 7. The image sensor of claim 6, wherein the logic circuit is configured to: (i) turn on the first enable element and the second enable element when an intensity of the light is less than a predetermined reference intensity, and (ii) turn off the first enable element and the second enable element when the intensity of the light is greater than the reference intensity.
 8. The image sensor of claim 6, wherein the logic circuit is configured to: (i) obtain a predetermined reference voltage through each of the first column line and the second column line after obtaining the reset voltage and the pixel voltage, and (ii) generate the image data based on a difference between the reference voltage and the reset voltage and a difference between the reference voltage and the pixel voltage.
 9. The image sensor of claim 6, wherein the logic circuit samples a first pixel voltage corresponding to electrical charge generated by the photodiode during a first exposure time, to the first primary capacitor and the first secondary capacitor in each of the plurality of pixels, and samples a second pixel voltage corresponding to electrical charge generated by the photodiode during a second exposure time to the second primary capacitor in each of the plurality of pixels; wherein the second exposure time is shorter than the first exposure time; and wherein, subsequent to the first exposure time, the logic circuit generates the image data based on the first pixel voltage and the second pixel voltage.
 10. The image sensor of claim 6, further comprising: a light source configured to irradiate light onto a subject, which reflects the light to the plurality of pixels; wherein the logic circuit is configured to: (i) store electrical charges generated by the photodiode in each of the plurality of pixels during a first exposure time at which the light source is turned on, in the first primary capacitor, (ii) store electrical charges generated by the photodiode in each of the plurality of pixels during a second exposure time in which the light source is turned off after the first exposure time, in the second primary capacitor, and (iii) generate the image data, based on a first pixel voltage corresponding to electrical charge generated by the photodiode during the first exposure time and a second pixel voltage corresponding to electrical charge generated by the photodiode during the second exposure time.
 11. The image sensor of claim 10, wherein the logic circuit is configured to turn off the first enable element and the second enable element during the first exposure time and the second exposure time.
 12. The image sensor of claim 1, further comprising: a first semiconductor substrate on which the photodiode and the pixel circuit are disposed; and a second semiconductor substrate on which the first output circuit and the second output circuit are disposed and stacked with the first semiconductor substrate.
 13. (canceled)
 14. An image sensor, comprising: a pixel array having a plurality of pixels therein; and a logic circuit configured to drive the pixel array in order to obtain image data therefrom, wherein each of the plurality of pixels includes: a photodiode configured to generate electrical charges in response to light; a transfer element electrically connected between the photodiode and a floating diffusion node, which accumulates the electrical charges generated by the photodiode; a driving element electrically connected to the floating diffusion node, said driving element configured to generate an output voltage by amplifying a voltage of the floating diffusion node; a first output circuit electrically connected between a first column line and the driving element, said first output circuit including a first switching element, a first capacitor electrically connected to the first switching element, and a first selection element electrically connected between the first capacitor and the first column line; and a second output circuit electrically connected between a second column line and the driving element, said second output circuit including a second switching element, a second capacitor electrically connected to the second switching element, and a second selection element electrically connected between the second capacitor and the second column line; and wherein the logic circuit is configured to set the first capacitor to have a first capacity when an intensity of the light is a first intensity, and set the first capacitor to have a second capacity, smaller than the first capacity, when the intensity of the light is a second intensity greater than the first intensity.
 15. The image sensor of claim 14, wherein when the intensity of the light is the first intensity, the logic circuit sets the second capacitor to have a third capacity, and when the intensity of the light is the second intensity, the logic circuit sets the second capacitor to have a fourth capacity smaller than the third capacity.
 16. (canceled)
 17. The image sensor of claim 14, wherein the first capacitor includes: a first primary capacitor, a first secondary capacitor having a capacity smaller than a capacity of the first primary capacitor, and a first enable element electrically connected between the first primary capacitor and the first secondary capacitor.
 18. The image sensor of claim 14, wherein the logic circuit includes a first analog-to-digital converter electrically connected to the first column line, and a second analog-to-digital converter electrically connected to the second column line, and is configured to obtain the image data based on a difference between a first digital signal output from the first analog-to-digital converter and a second digital signal output from the second analog-to-digital converter.
 19. An image sensor, comprising: a pixel array having a plurality of pixels therein; and a logic circuit configured to expose the plurality of pixels to light for an exposure time and obtain image data from the pixel array; wherein each of the plurality of pixels includes: (i) a photodiode, (ii) a pixel circuit connected to the photodiode and configured to generate a reset voltage and a pixel voltage, (iii) a first output circuit including a first capacitor for storing the reset voltage, and connected between a first column line and the pixel circuit, and (iv) a second output circuit including a second capacitor for storing the pixel voltage, and connected between a second column line and the pixel circuit; and wherein the logic circuit is configured to adjust a capacity of each of the first and second capacitors based on a duration of the exposure time.
 20. The image sensor of claim 19, wherein when the exposure time is longer than a predetermined reference time, the logic circuit sets a capacity of the first capacitor to be a first capacity, and when the exposure time is shorter than the predetermined reference time, the logic circuit sets the capacity of the first capacitor to be a second capacity, smaller than the first capacity.
 21. The image sensor of claim 20, wherein when the exposure time is longer than the predetermined reference time, the logic circuit sets a capacity of the second capacitor to be a third capacity, and when the exposure time is shorter than the predetermined reference time, the logic circuit sets the capacity of the second capacitor to be a fourth capacity smaller than the third capacity.
 22. The image sensor of claim 19, wherein during one frame period in which the logic circuit obtains the image data from the plurality of pixels, the exposure time includes a first exposure time and a second exposure time shorter than the first exposure time; and wherein the logic circuit is configured to connect the first output circuit to the pixel circuit, between the first exposure time and the second exposure time, and connect the second output circuit to the pixel circuit after the second exposure time. 23.-25. (canceled) 